Niosll-IP下自定义高速串行接口的设计与实现  

Design of Custom High-speed Serial Peripheral Interface in Multiple FPGA System

作　　者：雷瑞庭[1] 宋跃[1] 李兆国[1,2] 

机构地区：[1]东莞理工学院电子工程学院,广东东莞523808 [2]华南理工大学电子与信息学院,广州510640

出　　处：《东莞理工学院学报》2010年第1期47-50,共4页Journal of Dongguan University of Technology

基　　金：国家自然科学基金重大项目(10890095);广东省高等教育教学改革项目(BKJGYB2008096)

摘　　要：介绍了NiosII处理器的外设IP的设计方法,并详细介绍了用于多片FPGA间的命令、数据传输的自定义高速串行接口IP设计、验证和测试方法。该设计使用VerilogHDL语言完成硬件逻辑部分设计,对主从串行模块进行了详尽的协议设计,并编写了相关的驱动程序。实验表明该IP可被无缝整合到各种形式的SOPC嵌入式系统中。The design of custom high-speed serial peripheral interface base on FPGA was introduced. It could be used in transferring instruction or data among principal and subordinate modules in multiple FPGA system. The detailed communication protocol was designed. The program was written with verilog HDL and simulated successfully. It worked right for 25MHz in the reality testing. As an IP core, it could be transplanted to various forms of embedded systems after slightly modified.

关 键 词：NIOSII IP设计 串行数据接口 FPGA/SOPC VERILOG 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]