高密度三维封装技术  

High Density 3D Packaging Technology

作　　者：李秀清[1] 

机构地区：[1]河北半导体研究所

出　　处：《半导体情报》1998年第6期25-31,共7页Semiconductor Information

摘　　要：简要介绍为满足日益增长的低功耗、轻重量、小体积系统的应用需求而涌现出的多种裸芯片封装与多芯片叠层封装技术。详细讨论三维封装的垂直互连工艺。主要分析三维封装技术的硅效率、复杂程度、热处理、互连密度、系统功率与速度等问题。This paper introduces a number of bare and multichip module stacking technologies that are emerging to meet the ever increasing demands for low power consumption,low weight and compact systems.Vertical interconnect techniques are reviewed in details.Technological issues such as silicon efficiency,complexity,speed and power consumption etc.are briefly discussed.

关 键 词：三维封装 垂直互连 裸芯片叠层 半导体电路 

分 类 号：TN305.94[电子电信—物理电子学]