Recent Advance in Non-Krylov Subspace Model Order Reduction of Interconnect Circuits  

作　　者：Sheldon X.-D. Tan 

机构地区：[1]Department of Electrical Engineering, University of California

出　　处：《Tsinghua Science and Technology》2010年第2期151-168,共18页清华大学学报（自然科学版（英文版）

基　　金：Supported in part by National Science Foundation (NSF) (Nos.CCF-0448534 and OISE-0929699);in part by the National Natural Science Foundation of China (No. 60828008)

摘　　要：Model order reduction of interconnect circuits is an important technique to reduce the circuit complexity and improve the efficiency of post-layout verification process in the nanometer VLSI design. Existing works using the Krylov subspace method are very efficient, but the resulting models are less compact and lack global accuracy. Also, existing methods cannot handle interconnect circuits with large input and output ports. Recent advances in reduction techniques using non-Krylov subspace techniques such as truncated balanced realization （TBR） hold some promise to solve these problems. In this paper, we first review the classic TBR-based reduction methods and then present the recent developments in fast TBR-based reduction and techniques such as PMTBR, SBPOR, and ETBR methods. These newly proposed methods try to avoid the expensive computing steps in traditional TBR methods at some cost to accuracy to boost efficiency and scalability, which is critical to reduce large interconnect parasitics modeled as RLCK circuits. The ETBR method can also reduce circuits with massive ports by considering the input signals. We show the pros and cons of each method and compare them on a set of large interconnect circuits, and finally point to some new research directions for this area.Model order reduction of interconnect circuits is an important technique to reduce the circuit complexity and improve the efficiency of post-layout verification process in the nanometer VLSI design. Existing works using the Krylov subspace method are very efficient, but the resulting models are less compact and lack global accuracy. Also, existing methods cannot handle interconnect circuits with large input and output ports. Recent advances in reduction techniques using non-Krylov subspace techniques such as truncated balanced realization （TBR） hold some promise to solve these problems. In this paper, we first review the classic TBR-based reduction methods and then present the recent developments in fast TBR-based reduction and techniques such as PMTBR, SBPOR, and ETBR methods. These newly proposed methods try to avoid the expensive computing steps in traditional TBR methods at some cost to accuracy to boost efficiency and scalability, which is critical to reduce large interconnect parasitics modeled as RLCK circuits. The ETBR method can also reduce circuits with massive ports by considering the input signals. We show the pros and cons of each method and compare them on a set of large interconnect circuits, and finally point to some new research directions for this area.

关 键 词：model order reduction balanced realization INTERCONNECT 

分 类 号：TN402[电子电信—微电子学与固体电子学] O241.6[理学—计算数学]