可编程逻辑阵列分段递进优化布局算法研究  

A Research on Subsection Progressive Optimization Placement Algorithm of FPGA

作　　者：崔秀海[1] 杨海钢[1] 龚萧[1,2] 黄娟[1,2] 谭宜涛[1,2] 

机构地区：[1]中国科学院电子学研究所,北京100190 [2]中国科学院研究生院,北京100039

出　　处：《电子与信息学报》2010年第6期1395-1400,共6页Journal of Electronics & Information Technology

摘　　要：为了提高FPGA（Field Programmable Gate Array）的布通率并优化电路的连线长度,在模拟退火算法的基础上,该文提出一种新的FPGA布局算法。该算法在不同的温度区间采用不同的评价函数,高温阶段采用半周长法进行快速优化布局,低温阶段在评价函数中加入变量因子并进行适度的回火处理,以此来优化布局。实验表明,该算法提高了布通率,优化了连线长度,与最具代表性的VPR（Versatile Place and Route）布局算法相比布线通道宽度提高了近6%,电路总的连线长度降低了4-23%。A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires.Different cost functions are applied to different temperature range.In high temperature stage,the half perimeter method is utilized to fast optimize the placement;while in low temperature stage,a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement.Experiment results demonstrate that,compared with the VPR,the proposed method requires 6% fewer routing tracks and the length of wire is 4~23% shorter.

关 键 词：FPGA 布局 评价函数 布通率 模拟退火 VPR(Versatile PLACE and Route) 

分 类 号：TN432.2[电子电信—微电子学与固体电子学]