一种1.5～2μm双掺杂多晶硅栅CMOS工艺研究  

Study on a 1.5～2 μm Double Doped Poly Si Gate CMOS Process

作　　者：谭开洲[1] 胡永贵[1] 张家斌[1] 

机构地区：[1]电子工业部第二十四研究所

出　　处：《微电子学》1999年第2期119-122,共4页Microelectronics

摘　　要：采用常规Ｐ阱硅栅ＣＭＯＳ改进工艺，进行１．５～２μｍＣＭＯＳ工艺研究。与常规工艺相比，做出的ＰＭＯＳ管漏源击穿电压可达１８～２３Ｖ，５Ｖ工作电压下沟道调制效应较小，相应的欧拉电压可达２５～３０Ｖ，工艺特点在于采用了硼掺杂多晶硅作ＰＭＯＳ管栅电极，磷掺杂多晶硅作ＮＭＯＳ管栅电极。A 1.5～ 2 μm CMOS process is investigated based on a modified conventional p well Si gate CMOS process.The PMOS transistor fabricated with the modified process has a drain source breakdown voltage up to 18～ 23 V ,an Early voltage up to 25～30 V and a smaller channel modulation effect at 5 V operating voltage,compared with the conventional process.The point of the process lies in the use of boron doped polysilicon as the gate of PMOS transistors and phosphorous doped polysilicon as the gate of NMOS transistors.

关 键 词：CMOS工艺 多晶硅栅 PMOS晶体管 

分 类 号：TN386.405[电子电信—物理电子学]