FPGA电路动态老化技术研究  

Research of Dynamic Burn-in Test for FPGA IC

作　　者：郁振华[1] 朱卫良[1] 

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子与封装》2010年第7期24-27,共4页Electronics & Packaging

摘　　要：近年来,随着FPGA电路在军工和航天领域的广泛应用,用户对FPGA电路的可靠性要求也越来越高。在集成电路的可靠性评估试验中,动态老化试验是最重要的试验之一,FPGA动态老化技术的实现可以提高FPGA电路的可靠性。文章通过研究FPGA电路内部结构和功能模块,讨论FPGA电路加载配置过程的原理和流程,通过对动态老化和静态老化的对比试验和结果分析,研究出FPGA电路动态老化试验方法,并在工程实践中得到了成功实现和应用。Now FPGA integrated circuit has been used widely for the area of military and aerospace,therefore the reliability of the FPGA is more important to the customer.Dynamic burn-in test is the most important test in the reliability evaluation of integrated circuits.If the way of the FPGA Dynamic burn-in test can be realize,the reliability will be improved.In the paper,we study the configuration logic block and function block,discuss the principle and the flow for the configuration of FPGA integrated circuit,then we design a new method of dynamic burn-in test for FPGA,and now the method is implemented successfully and used in engineering.

关 键 词：可靠性 动态老化 FPGA 配置 

分 类 号：TN406[电子电信—微电子学与固体电子学]