静态随机存取存储器漏电流功耗降低技术  

Leakage Power Reduction Technology for SRAM

作　　者：吴晨[1] 张立军[1] 马亚奇 郑坚斌 

机构地区：[1]苏州大学电子信息学院,江苏苏州215006 [2]苏州秉亮科技有限公司,江苏苏州215021

出　　处：《微电子学》2010年第4期551-555,560,共6页Microelectronics

摘　　要：分析了静态随机存取存储器(SRAM)的漏电流,总结了目前业界所用的各种降低漏电流的技术,包括衬底偏压、源极偏压、双电源电压、字线电压反偏和位线电压浮动结构。它们都是通过改变SRAM各个端点的电压来实现的,在降低漏电流的同时,对SRAM器件性能也有一定的影响。基于UMC 55 nm CMOS工艺,对几种方案进行了仿真,并在理论分析的基础上,指出未来发展的趋势。Leakage current component of SRAM was analyzed.Different technologies for leakage current reduction were summarized,including body bias,source bias,dynamic VDD,negative word-line and bit-line floating schemes.In these technologies,voltages of SRAM at all ports in standby mode were regulated to reduce leakage current,which,however,had certain effects on the performance of SRAM.A number of low power technologies were simulated based on UMC＇s 55 nm CMOS process,and developing trend of the leakage current saving technology was discussed.

关 键 词：静态随机存取存储器 漏电流 功耗降低技术 

分 类 号：TN432[电子电信—微电子学与固体电子学]