基于CPLD/FPGA的任意分频器设计研究与仿真  

The Design and Simulation of Frequency Divider on CPLD/FPGA

作　　者：王耀琦[1] 王小鹏[1] 王静[1] 

机构地区：[1]兰州交通大学电子与信息工程学院,甘肃兰州730070

出　　处：《兰州交通大学学报》2010年第4期10-13,共4页Journal of Lanzhou Jiaotong University

基　　金：国家自然科学基金(60962004)

摘　　要：在介绍整数分频、半整数分频算法的基础之上,提出了小数分频的基本算法和改进算法,并通过VerilogHDL语言实现了编程,在QuartusⅡ环境下进行仿真实验,且在Altera公司的芯片EPM240T100I5上得到了实现.实验结果表明:在CPLD/FPGA上完全可以实现整数和半整数分频,也能实现统计平均意义上的小数分频.The basic and improved algorithms of decimal frequency are proposed on the basis of describing integer and half-integer frequency division algorithms,programming by Verilog HDL Language.The simulation test has been performed in Quartus Ⅱ,and the algorithm has been achieved on Altera＇s chips—EPM240T100I5.The test showes that the integer and half-integer frequency division can be achieved on the CPLD / FPGA,and the decimal frequency division can also be achieved on statistical average sense.

关 键 词：整数分频 半整数分频 小数分频 CPLD/FPGA VERILOG HDL QuartusⅡ 

分 类 号：TN772[电子电信—电路与系统]