基于FPGA的高精度全数字锁相环IP核设计  

Design of High-precision IP Core of All Digital Phase-locked Loop Based on FPGA

作　　者：杨秀增[1] 蒋志年[1] 

机构地区：[1]广西民族师范学院物理与信息技术系,广西崇左532200

出　　处：《计算机测量与控制》2010年第9期2127-2129,共3页Computer Measurement &Control

基　　金：广西壮族自治区教育厅科研项目(No.200911LX474);广西民族师范学院科研资助项目(No.zdxm200906)

摘　　要：全数字锁相环(ADPLL)在数字领域中得到广泛的应用;针对目前锁相环功能单一、设计不灵活和设计效率低等缺点,利用硬件描述语言设计了一个高精度全数字锁相环IP核,锁相环IP的中心频率和带宽均可任意编程设置,利用了Quartus II8.0中的嵌入式逻辑分析仪进行了验证;验证结果表明,该IP核运行稳定,锁相精度高,具有一定的实用性和推广价值。All-digital phase-locked loop has been widely applied in the digital domain.Considered the defects of present PLL,such as single,not flexible,and inefficient,a kind of high-precision IP core of all digital phase-locked loop is designed by hardware description language.Center frequency and bandwidth of the ADPLL are both arbitrarily set by software.SigalTap II Logic Analyzer in Quartus II8.0 is used to test validity.The test results shows that IP Core runs stably and accurately.There is practical and worthy of using abroad.

关 键 词：全数字锁相环 FPGA IP核 嵌入式逻辑分析仪 

分 类 号：TP306[自动化与计算机技术—计算机系统结构]