超高速低功耗CMOS 4:1复接器  

Ultrahigh-speed low-power CMOS 4:1 multiplexer

作　　者：冯军[1] 管忻[1] 李育军[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《高技术通讯》2010年第11期1196-1200,共5页Chinese High Technology Letters

基　　金：863计划(2001AA312010;2006AA01Z284)资助项目

摘　　要：研究了在特定工艺条件下进行高速低功耗集成电路设计的相关问题,包括结构设计、电路设计和工艺角的影响。提出用CMOS逻辑电路完成超高速电路设计的思想,利用CSM 0.35μm CMOS工艺设计完成了速率为3.125Gb/s的4:1复接器芯片。该系统采用树型结构,由两个并行的低速2:1复接单元和一个高速2:1复接单元级联而成。核心电路锁存器在低速单元中用带有电平恢复的4_T电路构成,在高速单元中用动态传输门构成;选择器则用CMOS传输门构成的双路开关实现,每一电路都只用4只晶体管实现。芯片面积为0.39mm^2。芯片测试结果表明:在3.3V电源电压下,芯片核心功耗低于40mW,最高工作速率可达4Gb/s。This paper is relating to the research on the subject of ultrahigh-speed low-power IC design in a certain process, including the framework design, the circuit design and the effect of comer. A 3. 125Gb/s 4：1 multiplexer implemented in the CSM 0.35/~m CMOS process is reported. The core circuits are realized using CMOS logic circuits. The system adopts the tree-type structure, and it is composed of two parallel low speed 2.1 multiplexers and a high speed 2：1 multiplexer. The level restoration 4 _ T circuit is proposed for the low speed cell while the dynamic transmission gate logic for the high speed cell. The selector adopts the CMOS transmission gate. Each of the core circuits takes 4 transistors only. The die area is 0.39mm2. The test results show that the core power consumption is lower than 40mW at a supply voltage of 3.3V. The highest rate of output data is up to 4Gb/s.

关 键 词：CMOS逻辑 复接器 超高速 低功耗 工艺角 

分 类 号：TN432[电子电信—微电子学与固体电子学]