基于Verilog-A的流水线ADC双余量曲线行为级建模  

Behavioral Modeling of Two-Residue Curve in Pipeline A/D Converter Based on Verilog-A

作　　者：罗敏[1] 王新胜[1] 尹帅[1] 

机构地区：[1]哈尔滨工业大学(威海)微电子中心,山东威海264209

出　　处：《微电子学》2010年第6期880-883,889,共5页Microelectronics

摘　　要：流水线ADC使用数字校正算法来提高精度。与传统的数字校正算法不同,基于统计的数字校正算法是在产生双余量曲线的基础上完成的,所以,双余量曲线的产生至关重要。Verilog-A为模拟电路提供了一种自顶向下的设计方法,在短时间内验证设计者的思想,提高工作效率。利用Verilog-A,对双余量曲线产生模块建模,采用Cadence的Spectre仿真器,对建立的行为模型进行仿真验证。Digital correction algorithm is usually used to improve resolution of pipelined A/D converter.Different from the conventional correction method,the statistics based digital correction method is realized by generating two-residue curves,which is very important.Modeling of two-residue generation circuit was done using Verilog-A,which could provide a top-down design method for analog circuit and system.And the established behavioral model was verified with Spectre of Cadence.

关 键 词：流水线A/D转换器 VERILOG-A 双余量曲线 

分 类 号：TN47[电子电信—微电子学与固体电子学]