沟槽栅功率MOSFET导通电阻的模拟研究  

Analysis of Power Trench MOSFET With Lower On-resistance

作　　者：王颖[1] 程超[1] 胡海帆[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,哈尔滨150001

出　　处：《北京工业大学学报》2011年第3期342-346,共5页Journal of Beijing University of Technology

基　　金：中央高校基本科研业务费专项资金资助(HEUCFT1008)

摘　　要：为了进一步降低沟槽栅功率MOS器件的导通电阻,提出了一种改进的trench MOSFET结构.借助成熟的器件仿真方法,详细分析了外延层杂质掺杂对器件导通电阻和击穿电压的影响,通过对常规trench MOSFET和这种改进的结构进行仿真和比较,得出了击穿电压和导通电阻折中效果较好的一组器件参数.模拟结果表明,在击穿电压基本相当的情况下,新结构的导通电阻较之于常规结构降低了18.8%.A new structure of trench MOSFET with lower on-resistance is proposed in this paper.The influence of epitaxy layer impurity concentration over on-resistance and breakdown voltage of the device is discussed in detail by device simulation.Parameters of an optimized device are obtained by simulation and comparison with traditional structure.It shows that the new structure of trench MOSFET achieves the reduction of the on-resistance by 18.8% in the on-state when compared with conventional trench MOSFET.

关 键 词：沟槽栅MOSFET 导通电阻 击穿电压 器件仿真 

分 类 号：TN342.4[电子电信—物理电子学]