可重构硬件内建自测试与容错机制研究  

Research on built-in self-test and fault-tolerant technology for digital reconfigurable hardware

作　　者：郝国锋[1] 王友仁[1] 张砦[1] 孙川[1] 

机构地区：[1]南京航空航天大学自动化学院,南京210016

出　　处：《仪器仪表学报》2011年第4期856-862,共7页Chinese Journal of Scientific Instrument

基　　金：国家自然科学基金(60871009);航空科学基金(2009ZD52045);南京航空航天大学基本科研业务费专项科研项目(NS2010086)

摘　　要：传统可重构硬件自测试方法复杂,容错时资源利用率低,且往往需要额外的软件配合处理器来实现。为此,设计了一种具有自测试与自主容错能力的新型可重构硬件结构。对于故障自测试,提出了能在线执行的自主循环测试方法;对于硬件容错,提出了分层自主容错机制:在功能细胞单元内测试到逻辑故障时,先用功能细胞单元内部的空闲基本逻辑单元替代故障基本逻辑单元;当没有空闲基本逻辑单元时,则将整个故障功能细胞单元的功能重配置到距其最近的空闲功能细胞单元中,实现两层容错。以6×6并行乘法器为例,验证了新型可重构阵列能够降低容错时间复杂度并提高冗余资源利用率。Conventional self-test methods of reconfigurable hardware are complex and have low utilization rate of resource.They often require additional software and processors.This paper designs a new online self-test and self-reconfigurable fault-tolerance array.On malfunction self-test,a circular self-test method that can execute online is proposed;on hardware fault-tolerance,hierarchical self fault-tolerance mechanism is proposed.When logical fault is tested in a functional cell,firstly,the spare basic logic elements（BLE） in the functional cell is used to replace the malfunction BLE;when there is no more spare BLE,the function of the malfunction cell is configured into the nearest spare cell.The implementation and simulation of a 6-bit parallel multiplier is presented to demonstrate that the new reconfigurable array can reduce the time complexity of fault-tolerance and improve the utilization rate of the redundancy resources.

关 键 词：数字电子系统 可重构硬件 细胞单元阵列 自主容错 内建自测试 并行乘法器 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]