基于FPGA雷达多目标模拟器DRFM设计与实现  

DRFM design for radar multi-target simulator based on FPGA

作　　者：刘魁[1] 颜学龙[1] 关世友[1] 赵志强[1] 

机构地区：[1]桂林电子科技大学电子工程学院,广西桂林541004

出　　处：《电子技术应用》2011年第5期52-55,共4页Application of Electronic Technique

基　　金：广西研究生教育创新计划资助项目(2010105950804M35)

摘　　要：研究了雷达多目标模拟系统中数字射频存储(DRFM)单元的设计与实现,根据模拟系统的设计要求,提出一种基于高性能FPGA数字射频存储单元设计方法;着重阐述了数字射频存储单元的设计思路,给出了系统的设计方案,并对系统中雷达模拟目标的各功能模块进行了分析,实验结果表明,所设计的DRFM满足设计系统要求。The problem of DRFM designing for radar multi-target simulator is discussed in this paper . According to the demand of radar simulator task, a new design approach based on FPGA and SDR technique is proposed. The design diagram and system performance analysis is presented in details. The compute formula of target distance error is derived. The prototype of DRFM is produced. Experiment result shows that the DRFM accomplished is identical to the design requirements.

关 键 词：雷达 模拟器 数字射频存储(DRFM) FPGA 

分 类 号：TN955[电子电信—信号与信息处理]