一种交错并行隐式刷新增益单元eDRAM设计  

Gain Cell eDRAM Design with Stagger Hidden Refresh Scheme

作　　者：孟超[1] 严冰[1] 林殷茵[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《半导体技术》2011年第6期466-469,486,共5页Semiconductor Technology

摘　　要：设计了一种与逻辑工艺兼容的64 kb高速高密度嵌入式增益单元动态随机存储器(eDRAM)。该存储器单元通过结构和版图的优化,典型尺寸为同代SRAM的40%。高低阈值管的引入分别改善了单元的读取速度和数据保持时间。同时交错并行隐式刷新机制利用增益存储单元读、写端口独立的结构和操作特性,配以合适的时序和仲裁机制,使得在无额外通信信号和握手接口下,实现刷新与访问互不影响,数据访问率达到100%。相比其他隐式刷新技术,该技术不需要过大的外围开销即可完成访问带宽加倍。芯片用SMIC 0.13μm CMOS工艺实现,大小为1.35 mm×1.35 mm。A 64 kb logic compatible gain cell embedded DRAM（eDRAM）was demonstrated for high speed and high density applications.By optimizing the cell structure and layout,the cell size is typically 60% smaller than that of an SRAM cell with the same technology.High Vt and low Vt PMOS transistors were adopted in Qw and Qr respectively in order to improve read speed and data retention time.Meanwhile,based on independent read/write path and operation characteristics of gain cells,the stagger hidden refresh scheme was proposed with appropriate timing and arbitration.Therefore,the periodic refresh was transparent to access operations,which couldn＇t require explicit control signal and handshake communication between memory and external accessing client.In addition,100% data availability can be achieved.Compared with other hidden refresh techniques,the data bandwidth can be doubled without significant peripheral overburden.The design was fabricated on SMIC 0.13 μm CMOS process with 1.35 mm×1.35 mm chip size.

关 键 词：嵌入式 增益单元 动态随机存储器 交错并行隐式刷新 数据访问率 

分 类 号：TP333.8[自动化与计算机技术—计算机系统结构] TN432[自动化与计算机技术—计算机科学与技术]