基于VHDL语言的数字时钟设计  

Design of digital clock based on VHDL language

作　　者：李晓敏[1] 田熙燕[1] 

机构地区：[1]河南科技学院机电学院,河南新乡453003

出　　处：《电子设计工程》2011年第13期30-32,35,共4页Electronic Design Engineering

基　　金：2010年度河南省科技计划项目(102102210190)

摘　　要：介绍了VHDL语言的特点及优势,表明了EDA技术的先进性,采用自上而下的设计思路,运用分模块的设计方法设计了数字时钟系统,并在QuartusⅡ环境下进行编译和仿真,完成了24 h计时和辅助功能设计,证明了方案的可行性,体现出了"硬件设计软件化"的新趋势。This article introduces the characteristics of the VHDL language,and shows the advanced EDA technology.In this paper,the top-down hierarchical design method to design a digital clock system is adopted,and the system is compiled and simulated under QuartusⅡ.It shows that the system has the feature as a digital clock.It confirms that this design method is practical and feasible,and it also shows the new trends of ＂hardware design to software design＂.

关 键 词：EDA技术 数字时钟 VHDL 设计 

分 类 号：TN702[电子电信—电路与系统]