基于PXIE总线的高速CCD数字图像采集系统设计  

Design of High-speed CCD Digital Image Collecting System Based on PXIE Bus

作　　者：霍志[1] 刁节涛[1] 李清江[1] 邢金岭[1] 刘海军[1] 

机构地区：[1]国防科学技术大学嵌入式系统与固态存储工程研究中心,湖南长沙410073

出　　处：《现代电子技术》2011年第14期88-92,共5页Modern Electronics Technique

摘　　要：为实现高速电容耦合器件(CCD)数字图像采集传输,提出一种基于PXIE总线和Camera Link协议的高速图像采集系统设计方案。设计了Camera Link硬件接口电路,实现了视频数据信号的接口设计、控制信号的接口设计、串行通信信号接口设计;同时采用Xilinx公司的Virtex-5 LX50T型FPGA作为PXIE传输控制器,并对IP核进行了开发,减少了外围电路设计难度。创新性地运用直接内存访问的工作方式对PXIE传输速度进行优化。实验结果表明,PXIE配置为8通道时,读取数据速率达到1 504 MB/s,写入速率达到了1 490 MB/s,可以满足高速CCD数据的传输要求。A design scheme of high-speed image collecting system based on PXIE bus and Camera Link protocol is pro- posed to realize the high-speed CCD （capacitive coupled device） digital image acquisition transmission. The interface circuit of the Camera Link protocol is designed. The designs of video data signal interface, the control signals interface and the serial communication signal interface are implemented. The Xilinx Virtex-5 LX50T FPGA is used as the transmission control device of PXIE bus, and IP core is developed to reduce the difficulty of the peripheral circuit design. The DMA （direct memory ac- cess） method is innovately adopted to optimize the transmission speed of PXIE. The results show that, while PXIE is con- figured with 8-channel, the read data rate is up to 1504 MB/s, the write data rate is up to 1490 MB/s, which meet the re- quirements of high-speed CCD data transmission.

关 键 词：PXIE CAMERA LINK IP核 CCD DMA 

分 类 号：TN919-34[电子电信—通信与信息系统]