实时校正时间误差的Farrow结构滤波器设计  

Design of Farrow structure filter for realtime correction of time error

作　　者：秦小芳[1] 龙兵[1] 曾浩[1] 潘卉青[1] 

机构地区：[1]电子科技大学自动化工程学院,成都611731

出　　处：《电子测量技术》2011年第8期27-30,共4页Electronic Measurement Technology

摘　　要：实现1种基于Farrow结构分数时延(Fractional Delay,FD)滤波器对并行采样中时间非均匀误差的实时校正。采用优化设计的方法,求解Farrow结构FD滤波器的各子滤波器系数,在尽可能资源消耗少的情况下,使设计偏差较小,保证后续时延误差估计和校正的精度,并在Xilinx的FPGA中实现时间误差的校正。理论分析和实验结果表明本算法具有稳定性,算法所设计滤波器可用于动态时间补偿,所设计滤波器结构简单,资源消耗少,易于在硬件中实现,且校正效果明显。Discussed the digital post-processing technology of Farrow structure fractional delay filter,and corrected the sampling clock non-uniform of time error.Calculated coefficients of each branch of FD filter through adopting the optimization design way.Coefficients are fixed.Only need to change the time error which can be realized.This paper through simulation and FPGA hardware realization,verifies the feasibility of this method.Theoretical analysis and experimental results show that the algorithm has stability.The design of filter algorithm can be used in the dynamic time compensation.The filter structure is simple,and easy to realize in hardware.

关 键 词：FARROW结构 FD滤波器 FPGA 最优化方法 VERILOG HDL 

分 类 号：TP2[自动化与计算机技术—检测技术与自动化装置]