An improvement to computational efficiency of the drain current model for double-gate MOSFET  

作　　者：周幸叶 张健 周致赜 张立宁 马晨月 吴文 赵巍 张兴 

机构地区：[1]TSRC,Institute of Microelectronics,School of Electronic Engineering and Computer Science,Peking University [2]Academy for Advanced Interdisciplinary Studies,Peking University [3]Peking University Shenzhen SOC Key Laboratory,PKU-HKUST Shenzhen Institution

出　　处：《Chinese Physics B》2011年第9期392-395,共4页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China (Grant No.60876027);the National Science Foundation for Distinguished Young Scholars of China (Grant No.60925015);the National Basic Research Program of China (Grant No.2011CBA00600);the Fundamental Research Project of Shenzhen Science & Technology Foundation,China (Grant No.JC200903160353A)

摘　　要：As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

关 键 词：computational efficiency compact model DOUBLE-GATE MOSFET 

分 类 号：TN386.1[电子电信—物理电子学] TN386