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作 者:黄卓和[1]
机构地区:[1]广州师范学院物理系
出 处:《压电与声光》1990年第4期29-32,36,共5页Piezoelectrics & Acoustooptics
摘 要:本文从理论上解释了由半导体晶粒间的绝缘晶界以及晶界两侧的SI结和IS结势垒三者组成的晶界层电容,在低偏压下的C-V特性.指出了绝缘晶界和结势垒对C-V特性的不同影响,分析了高偏压下C-V和I-V特性相关性的物理本质.The C-V characteristics of grain boundary banier layer (GBBL) capacitors which are formed by insulation grain boundaries among semiconductor grains and baniers of the SI and IS junctions at the boundaries were eluciated theoretically in the case of both low and high biased valtage. The different influences of the insulation grain boundaries and the junction barnes on the C-V charaeteristics were indicated and the physical nature of the C-V and T-V correlation was analysed.
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