衬底寄生电阻对高压器件ESD性能的影响  

Effects of Substrate Parasitic Resistance on ESD Performance of High-Voltage Device

作　　者：林丽娟[1] 喻钊[1] 韩山明[1] 蒋苓利[1] 张波[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2011年第5期766-769,共4页Microelectronics

基　　金：国家自然科学基金资助项目(60906038)

摘　　要：随着高压集成电路的广泛应用,高压器件的ESD性能越来越受广大设计者的重视。从理论上分析了衬底寄生电阻对高压LDMOS器件ESD特性的影响,采用几种结构,对上述参数进行优化,并在0.35μm BCD工艺下进行流片试验。测试结果表明,优化衬底电阻可以有效地提高器件的ESD泄放能力,最优结构的二次击穿电流由原始器件的0.75A增大到3.3A。Effects of substrate parasitic resistance on ESD performance of LDMOS device were analyzed.A variety of structures were used to optimize the device,and the chosen structure was taped out in 0.35 μm BCD process.Test results showed that the optimized structures could effectively improve ESD robustness of the device and the secondary breakdown current of the optimal structure increased from 0.75 A of the original device to 3.3 A.

关 键 词：ESD 高压器件 衬底寄生电阻 

分 类 号：TN406[电子电信—微电子学与固体电子学]