应用于SoC的全数字锁相环ASIC设计  

The ASIC design of an all-digital phase-locked loop used in SoC system

作　　者：季轩[1] 毛陆虹[1] 王子青[1] 王峥[1] 陈力颍[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《电路与系统学报》2011年第5期8-13,共6页Journal of Circuits and Systems

基　　金：863计划重大项目(2008AA04A102);国家科技重大专项(2010ZX03007-002-03)

摘　　要：设计了一种全数字锁相环(All-Digital PLL)。该锁相环中环形数控振荡器由使能单元构成,且环形结构分为粗调和精调两部分,具有锁定范围宽、锁定精度高、功耗低的特点,且捕获范围可以根据需要进一步拓宽。本设计基于CMOS标准单元,所有子模块均采用可综合的Verilog HDL代码描述,利于不同工艺间的移植,设计周期和复杂度大大降低。该全数字锁相环可以产生不同频率的高精度时钟信号,作为IP嵌入SoC系统。An all-digital phase-locked loop is presented.The ADPLL has a ring digital-controlled oscillator composed by enabled units,with the ring structure divided into two parts in terms of the coarse tuning part and the fine tuning part.It includes the characteristic of wide locking range,high locking resolution,and low power consumption.What＇s more,the locking range can be further expended according to the demand.The design is based on CMOS standard cells and used synthesizable Verilog HDL for sub-modules description,so it can be easily implanted to different processes,and both the design time and complexity can be reduced.This design can provide a high resolution clock with different frequencies,used as a intellectual property（IP） block embedded in a SoC system.

关 键 词：全数字锁相环 数控振荡器 标准单元 IP核 VERILOG HDL 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]