基于FPGA的曼彻斯特编解码器设计  

Design of manchester codec based on FPGA

作　　者：汤晓曦[1] 尹蕾[1] 许晏[1] 陈泉根[1] 

机构地区：[1]中国工程物理研究院电子工程研究所,四川绵阳621900

出　　处：《电子设计工程》2011年第23期171-173,177,共4页Electronic Design Engineering

摘　　要：自上世纪80年代以来,MIL-STD-1553B总线标准已广泛应用于海陆空三军,但是其核心编解码芯片多为国外生产,为实现自主研发,设计出基于FPGA的曼彻斯特编解码器是影响整个总线系统通信质量的关键。本设计采用硬件描述语言(Verilog)设计电路,ISE完成综合和布局布线的工作,并用modelSim进行仿真验证。在深入分析曼彻斯特码型特点的基础上,对编解码器的工作过程和逻辑结构进行详细介绍。MIL-STD-1553B Bus standard has been widely used in Air force, navy and land force of many country since 1980s. The core encode and decode chip are gotten by import, in order to realize research and produce independently, whether designing the Manchester codec or not is the key to decide the communication quality of the whole 1553B bus. The codec is design by Verilog HDL, synthesized by ISE and simulated by ModelSim. On the basis of analyzing the characteristic of the Man2chester code , the principle and the circuit structure of the codec are introduced in detail.

关 键 词：MIL-STD-1553B总线 曼彻斯特码 FPGA VERILOG 

分 类 号：TN919.64[电子电信—通信与信息系统]