ASIC物理设计中的时钟树综合优化研究  

Optimization of Clock Tree Synthesis in Physical Design of ASIC's

作　　者：潘静[1] 吴武臣[1] 侯立刚[1] 彭晓宏[1] 

机构地区：[1]北京工业大学电子信息与控制学院集成电路与系统集成实验室,北京100124

出　　处：《微电子学》2011年第6期872-875,共4页Microelectronics

基　　金：国家自然科学基金资助项目(60976028)

摘　　要：以一款基于HJTC 0.18μm工艺的YAK SOC芯片为例,根据其时钟结构,提出一种能有效减小时钟偏移的方法,该方法通过在门级将时钟根节点分解成若干伪时钟源实现。基于该方法,采用布局布线工具,对YAK SOC芯片进行时钟树综合,得到了较好的效果。给出了一种采用缓冲器和反相器相结合构建时钟树以降低时钟树功耗的方法。通过完成物理设计和功耗分析的数据对比,证明了该优化方法的可行性。Based on the clock structure of a 0.18 μm YAK SOC chip,a method was presented to effectively reduce clock skew,in which the original clock root was divided into several pseudo clock sources at gate level.With this method,clock tree synthesis was made on a YAK SOC chip using planning and routing tools,and good results were achieved.Also,a method was proposed to reduce the power of the clock tree by designing clock tree with buffer and inverter.This method was validated by comparing data of physical design and power estimation.

关 键 词：深亚微米 专用集成电路 片上系统 时钟偏移 时钟树综合 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN402