一种基于值预测和指令复用的按序处理器预执行机制  

A Pre-Execution Mechanism Based on Value Prediction and Instruction Reuse for In-Order Processors

作　　者：党向磊[1] 王箫音[1] 佟冬[1] 陆俊林[1] 易江芳[1] 王克义[1] 

机构地区：[1]北京大学微处理器研究开发中心,北京100871

出　　处：《电子学报》2011年第12期2880-2883,共4页Acta Electronica Sinica

基　　金：国家863高技术研究发展计划(No.2006AA010202);中国博士后科学基金资助项目(No.20110490208)

摘　　要：为提高按序处理器的性能和能效性,本文提出一种基于值预测和指令复用的预执行机制(PVPIR).与传统预执行方法相比,PVPIR在预执行过程中能够预测失效Load指令的读数据并使用预测值执行与该Load指令数据相关的后续指令,从而对其中的长延时缓存失效提前发起存储访问以提高处理器性能.在退出预执行后,PVPIR通过复用有效的预执行结果来避免重复执行已正确完成的指令,以降低预执行的能耗开销.PVPIR实现了一种结合跨距(Stride)预测和AVD(Address-Value Delta)预测的值预测器,只记录发生过长延时缓存失效的Load指令信息,从而以较小的硬件开销取得较好的值预测效果.实验结果表明,与Runahead-AVD和iEA方法相比,PVPIR将性能分别提升7.5%和9.2%,能耗分别降低11.3%和4.9%,从而使能效性分别提高17.5%和12.9%.To improve the performance and energy-efficiency of in-order processors,this paper proposes a novel hardware mechanism,pre-execution based on value prediction and instruction reuse（PVPIR）.If a load instruction incurs a long-latency cache miss,PVPIR predicts its data value and uses the predicted value to pre-execute the following dependent instructions,including loads that incur long-latency misses,thus improving the performance.To reduce the energy consumption,PVPIR reuses the valid pre-executed results and thus avoids the re-execution of completed instructions.PVPIR also implements a hybrid value predictor which is a combination of stride prediction and address-value delta（AVD） prediction.The predictor only records history value for loads that have incurred long-latency misses,thus gaining good prediction results with little overhead.Experimental results demonstrate that PVPIR improves the performance by 7.5% and 9.2% while decreases the energy consumption by 11.3% and 4.9%,thus improving the energy-efficiency by 17.5% and 12.9%,as compared to Runahead-AVD and iEA,respectively.

关 键 词：预执行 值预测 指令复用 访存延时包容 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]