一种10位50MHz流水线模数转换器的设计  

Design of 10 Bit 50 MHz Pipelined A/D Converters

作　　者：王林锋[1] 周建伟[1] 甘小伟[1] 刘利宾[1] 邢少川[1] 

机构地区：[1]河北工业大学微电子研究所,天津300130

出　　处：《半导体技术》2012年第2期122-125,共4页Semiconductor Technology

摘　　要：采用每级1.5 bit和每级2.5 bit相结合的方法设计了一种10位50 MHz流水线模数转换器。通过采用自举开关和增益自举技术的折叠式共源共栅运算放大器,保证了采样保持电路和级电路的性能。该电路采用华润上华(CSMC)0.5μm 5 V CMOS工艺进行版图设计和流片验证,芯片面积为5.5 mm2。测试结果表明:该模数转换器在采样频率为50 MHz,输入信号频率为30 kHz时,信号加谐波失真比(SNDR)为56.5 dB,无杂散动态范围(SFDR)为73.9 dB。输入频率为20 MHz时,信号加谐波失真比为52.1 dB,无杂散动态范围为65.7 dB。A 10 bit 50 MHz pipelined ADC was presented by using the architecture of 1.5 bit/stage and 2.5 bit/stage. The gain-boosting folded cascade operationd amplifier and bootstrap switch were used to guarantee the performance of the sample and hold circuit and the sub-stages. The ADC was fabricated in the CSMC 0.5 um CMOS process under the 5 V voltage. The chip area is 5.5 mm2. The measured results indicate that the ADC exhibit 56..5 dB SNDR, 73.9 dB SFDR for 30 kHz input frequency at 50 MHz and 52. 1 dB SNDR, 65.7 dB SFDR for 20 MHz ioput frequency at 50 MHz.

关 键 词：流水线模数转换器 采样保持电路 运算放大器 自举开关 增益自举 

分 类 号：TN792[电子电信—电路与系统]