Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET  

Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET

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作  者:Mei Bo Bi Jinshun Li Duoli Liu Sinan Han Zhengsheng 梅博;毕津顺;李多力;刘思南;韩郑生(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)

机构地区:[1]Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China

出  处:《Journal of Semiconductors》2012年第2期36-40,共5页半导体学报(英文版)

基  金:supported by the National Natural Science Foundation of China(No.60927006);the Major Projects of National Science and Technology

摘  要:The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.

关 键 词:BACK-GATE threshold voltage STRESS SILICON-ON-INSULATOR 

分 类 号:TN386.1[电子电信—物理电子学]

 

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