一种低成本光接收器的数据恢复电路的设计及FPGA实现  

A Low-cost Optical Receiver Data Recovery Circuit Design and FPGA Implementation

作　　者：宁少春[1] 

机构地区：[1]重庆邮电大学光电学院,重庆400065

出　　处：《电子质量》2012年第4期26-28,共3页Electronics Quality

摘　　要：设计了一种利用FPGA的可编程输入延时单元(IDELAY)和锁相环输出同频多相时钟结合的4倍过采样高速时钟数据恢复电路。可在较低频率同步恢复4位并行数据,有效地增大带宽并降低了终端成本,并采用自动检测和判断的方法检测数据跳变边沿,消除了数据毛刺的干扰。Designed a FPGA programmable input delay unit（IDELAY） and phase-locked loop output combination with the frequency multi-phase clock four times over-sampling of high-speed clock and data recovery circuit.Recovery in the four parallel data at lower frequencies,effectively increase bandwidth and reduce the cost of the terminal,and automatically detect and determine the method detection data transition edge,eliminate the interference of data glitches.

关 键 词：时钟数据恢复 过采样 输入延时单元 现场可编程逻辑阵列 

分 类 号：TN851[电子电信—信息与通信工程]