超深亚微米物理设计中天线效应的消除  

Process Antenna Effect Elimination in Ultra Deep Submicron Physical Design

作　　者：张智胜[1] 吴秀龙[1] 

机构地区：[1]安徽大学微纳电子器件与集成电路设计省级实验室,合肥230601

出　　处：《半导体技术》2012年第6期429-432,共4页Semiconductor Technology

基　　金：安徽省教育厅重点科研项目(KJ2010A022)

摘　　要：分析了超深亚微米物理设计中天线效应的产生机理以及基于超深亚微米工艺阐述了计算天线比率的具体方法。同时,根据天线效应的产生机理并结合时钟树综合提出了消除天线效应的新方法。此方法通过设置合理的约束进行时钟树综合,使得天线效应对时钟延时和时钟偏斜的影响降到最低,从而对芯片时序的影响降到最低。最后结合一款芯片的物理设计,该设计采用台积电(TSMC)65 nm低功耗(LP)工艺,在布局布线中运用所述的方法进行时钟树综合并且使得时钟网络布线具有最大的优先权。此方法有效地消除了设计中存在的天线效应,并且使得天线效应对时钟树的影响降到最低以及对时序的影响降到最小。The mechanism of process antenna effect in ultra deep submicron physical design was analyzed and the antenna ratio calculation method which was based on the ultra deep submicron process was provided. A new elimination method of process antenna effect combined with clock tree synthesize was proposed. The elimination method minimized the impact on the clock latency and clock skew by setting up reasonable constraint for clock tree synthesize, so as to reduce the impact on timing of the chip to the lowest. Finally, the elimination method was used for clock tree synthesize during place and route of the physical design of a chip which was based on TSMC 65 nm low power （LP） technology and the routing of clock tree network had the most priority. The method eliminated the process antenna effect of the design effectively, and minimized the impact to clock tree and chip timing to the least.

关 键 词：超深亚微米 天线效应 时钟树综合 时序 布局布线 

分 类 号：TN402[电子电信—微电子学与固体电子学]