基于IEEE 1500并行测试技术的研究  

Research on parallel test technology based on IEEE 1500

作　　者：江志强[1] 邓洪高[2] 颜学龙[1] 柴华[1] 

机构地区：[1]桂林电子科技大学电子工程与自动化学院,广西桂林541004 [2]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《桂林电子科技大学学报》2012年第3期204-207,共4页Journal of Guilin University of Electronic Technology

基　　金：广西研究生教育科研创新计划(2010105950804M33)

摘　　要：针对现代IP核测试需要更高的测试效率,提出一种基于1500标准的并行测试方法。通过对1500中的边界寄存器与指令寄存器的重新设计,使它支持标准中强制规定的串行测试和用户可自定义的并行测试。在以74LS245外壳设计为例,通过Quartus II软件进行串并行的外测试仿真以及PSpice软件进行串并行内测试仿真,其结果表明,并行接口测试比串行接口测试提高数倍的效率,而且选择的测试方案较多,用户可以选择较优的测试方案。In view of the question that the modern IP core testing must be more efficiency, a parallel testing method based on the IEEE 1500 standard is proposed. After redesigning the wrapper boundary register and wrapper instruc- tion register, they can support the serial test which is mandatory in the standard and the parallel test which is the user defined. Taking the 74LS245 as an example, simulating the serial and parallel testing of the external test through the Quartus II software ,and simulating the internal test through the PSpice software ,the results show that the parallel interface testing is more efficiency than the serial interface ,and there are more test projects for users to choose.

关 键 词：并行测试 串行测试 IP核 

分 类 号：TP206[自动化与计算机技术—检测技术与自动化装置]