一种64位Booth乘法器的设计与优化  

Design and Optimization of 64-bit Booth Multiplier

作　　者：何军 朱英 

机构地区：[1]上海高性能集成电路设计中心,上海201204

出　　处：《计算机工程》2012年第16期253-254,共2页Computer Engineering

摘　　要：针对国产多核处理器的64位整数乘法器面积和功耗开销大的问题,提出一种新的Booth编码方式,对其Booth编码方式进行优化,通过多种方法验证设计优化的正确性,采用标准单元库进行逻辑综合评估。结果表明,工作频率可达1.0 GHz以上,面积减少9.64%,动态功耗和漏电功耗分别减少6.34%和11.98%,能有效减少乘法器的面积和功耗,达到预期目标。In order to solve the issue of large area and power dissipation overhead of the 64-bit integer multiplier of the homebred multi-core processor, the Booth encoding algorithm is optimized and a new Booth encoding is put forward. The correction of the optimized design is verified through multiple methods, and the design is logic synthesized based on standard cell library. As is turned out that the design can work at 1.0 GHz at least, its area is reduced by 9.64% and its dynamic and leakage power dissipation is decreased by 6.34% and 11.98%, which means the optimization can decrease the area and power consumption of multiplier effectively as expected.

关 键 词：BOOTH编码 并行乘法器 64位乘法器 设计优化 功耗 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]