低失配GaAs HBT 1.5bit高速模数转换器设计  

Design of Low Offset GaAs HBT 1.5 bit High Speed ADC

作　　者：林庆良[1] 吴旦昱[1] 周磊[1] 刘新宇[1] 金智[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《半导体技术》2012年第9期684-688,共5页Semiconductor Technology

摘　　要：介绍了一款基于GaAs HBT工艺的1 GS/s 1.5 bit模数转换器。通过分析模数转换器(ADC)的参考电压失配的来源,引入一种能提高电路对称性的新型差分参考网络架构,提出了减小失配的设计方法,显著提高了参考电平的对称性和一致性,从而减小参考电平的失配。此外,分析了比较器的静态和动态失配电压,对迟滞现象进行了解释。针对ADC的特点,详细分析了新型差分参考网络和比较器的关键设计参数。芯片实测结果表明,片内参考电平失配不超过1 mV,采样频率达到1 GS/s,功耗为350 mW。Based on GaAs HBT process,a 1 GS/s 1.5 bit ADC was introduced.By the analysis of the ADC reference voltage mismatch sources,a new type of symmetry that can improve circuit differential reference network structure was introduced.In order to improve the reference level of consistency and symmetry and reduce reference level of the mismatch,the design method of reducing mismatch was present.In addition,the comparator static and dynamic mismatch voltage were analyzed,and the hysteresis phenomenon was explained.According to the characteristics of the ADC,the novel difference reference network and the comparator key design parameters were analyzed.The chip test results show that mismatch is no more than 1 mV in reference level,the sampling frequency reaches 1 GS/s,and the power consumption is 350 mW.

关 键 词：高速信号采集 砷化镓电路 模数转换电路 比较器 低失配 迟滞电压 

分 类 号：TN792[电子电信—电路与系统]