基于数据预取的多核处理器末级缓存优化方法  

Data Prefetching Based Last-Level Cache Optimization for Chip Multiprocessors

作　　者：单书畅[1,2] 胡瑜[1] 李晓维[1] 

机构地区：[1]中国科学院计算技术研究所计算机体系结构国家重点实验室,北京100190 [2]中国科学院研究生院,北京100049

出　　处：《计算机辅助设计与图形学学报》2012年第9期1241-1248,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家"九七三"重点基础研究发展计划项目(2011CB302503);国家自然科学基金(61076018;60803031;60921002)

摘　　要：末级缓存的性能已成为影响多核处理器整体性能的关键因素.基于多核处理器在处理并行程序时各处理器核访存行为的相似性,提出一种降低访存缺失率的数据预取方法.首先记录各处理器核的访存缺失历史;然后通过分析历史信息预测各处理器核之间末级缓存缺失的关联关系,采用数据预取的方式,在处理器核出现读缺失之前为其末级缓存提供数据块.实验结果表明,对于4核和16核处理器系统,该方法可以分别降低末级缓存缺失率9.8%和18.4%,提高性能4.0%与12.4%.The performance of last-level cache （LLC） has become a key factor affecting the overall performance of chip multiprocessors （CMP）. Based on the LLC miss behaviorsimilarity among different nodes of the CMP system that processes parallel workloads, a data prefetching meehanism is proposed to significantly reduce the LLC miss rate. This paper starts from tracing the LLC miss behaviors, which is then utilized to identify the inter-core load miss correlation. In case of an load miss, if it is predieted to be followed by any further successive load misses of other nodes, the data block is simulteanously forwarded to the potential missing nodes. Experimental results demonstrate that, the proposed mechanism reduces the LLC miss rate by 9.8% and 18.4%, while improves the overall performance by 4.0% and 12.4% when eonsidering 4-core and 16-eore CMP systems.

关 键 词：多核处理器 末级缓存 并行程序 数据预取 

分 类 号：TP306.2[自动化与计算机技术—计算机系统结构]