金属栅回刻平坦化技术  

Novel Planarization Technology of Metal Gate Etch-Back in Advanced CMOS Fabrication

作　　者：孟令款[1] 殷华湘[1] 徐秋霞[1] 陈大鹏[1] 叶甜春[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《真空科学与技术学报》2012年第9期793-797,共5页Chinese Journal of Vacuum Science and Technology

基　　金：极大规模集成电路制造技术及成套工艺(02专项)(No.2009ZX02035);国家自然科学基金项目(No.60776030);中国科学院微电子器件与集成技术重点实验室课题资金资助

摘　　要：随着CMOS集成电路技术节点缩减到45 nm及以下,高K金属栅(HK/MG)的后栅集成工艺已逐渐成为先进集成电路制造中的主流技术。其中金属栅(假栅)集成结构的平坦化是实现后栅集成的关键技术之一。本文通过特色开发的SOG两步等离子体回刻结合O2原位处理技术,克服了常规反应离子刻蚀中由于聚合物分布不均对刻蚀速度带来的不利影响,实现了隔离绝缘层低达4.19%(边缘去除5 mm)的片内非均匀性。不同稀疏与密集线阵列的亚微米CMOS后栅结构表明良好的平坦化效果并且避免了类似CMP(Chemical Mechanical Polish)工艺中常出现的"碟形效应"问题。所研制成功的无CMP后栅平坦化工艺为制备纳米级高K金属栅CMOS后栅器件打下了重要基础。A novel technique was developed to effectively planarize the high-K metal gate etch-back in the advanced CMOS fabrication,where the feature size is scaled down to 45 nm.In the newly-developed technique,the two-step spin-on-glass plasma etch-back was combined with in-situ oxygen plasma treatment.The negative effect of the non-uniform distribution of the polymer on the reactive ion-etching rate was eliminated.As a result,the thickness non-uniformity within-the-wafer（excluding the 5 mm wafer edges） can be easily realized.In the scanning electron micrographs of the planarized metal gate etch-back,no chemical-mechanicalpolish-like ＂dish effect＂ was observed on both the isolated and the dense sub-micro gate-stack structures,indicating that the planarization technology does a good job for the nano-scale high-K /metal gate-last CMOS device integration.

关 键 词：金属栅 假栅 旋转涂布玻璃 等离子回刻 平坦化 

分 类 号：TN405[电子电信—微电子学与固体电子学]