一种兼容AMBA总线的实时高效静态存储管理IP的设计与实现  

Design and Implementation of a Real Time and High Performance Static Memory Controller IP Compatible with AMBA Bus

作　　者：王文丞[1] 奉世玉[1] 陈川[1] 聂泽东[1] 王磊[1] 

机构地区：[1]中国科学院深圳先进技术研究院,广东深圳518055

出　　处：《微电子学与计算机》2012年第10期140-143,147,共5页Microelectronics & Computer

摘　　要：设计了一种兼容AMBA2.0AHB总线的实时高效存储管理IP——静态存储管理IP.与虚拟存储管理技术相比,IP可以为实时系统芯片的高实时性提供良好的保障,它完成一次存储器访问最多需要2个时钟延时,最少可以达到0延时传输.同时它具有结构简单、可支持8个64M的静态存储器、可编程控制以及进行不同数据宽度的Burst传输等特点.设计采用结构完全并行、时序完全同步的状态机设计思想,采用SIMC.18工艺进行流片,系统芯片整体面积为5mm×3.5mm,测试结果与设计目标基本一致.A static memory controller IP compatible with AMBA2.0 bus was designed. Compared with virtual memory management, this IP highly enhanced the real-time ability of a real-time system chip since the maximum delay of one access was two clock cycles and the minimum delay was zero. Meanwhile this IP was with a simple structure and supported eight configurable 64 MB banks to control different static memories. A structure-paralleled and timing-synchronous design was adopted. The static memory controller was implemented with SMIC 0.18 μm process and the whole SoC area was 5 turn X 3.5 ram. The test results were in good agreement with the design specification.

关 键 词：实时系统芯片 静态存储管理 AMBA2.0 AHB总线 VERILOG HDL 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]