AN EFFICIENT 3-DIMENSIONAL DISCRETE WAVELET TRANSFORM ARCHITECTURE FOR VIDEO PROCESSING APPLICATION  

作　　者：Ganapathi Hegde Pukhraj Vaya 

机构地区：[1]Department of ECE, Amrita Vishwa Vidyapeetham, Amrita School of Engineering

出　　处：《Journal of Electronics(China)》2012年第6期534-540,共7页电子科学学刊（英文版）

摘　　要：This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0.45 W.This paper presents an optimized 3-D Discrete Wavelet Transform （3-DDWT） architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal （9/7） wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally im- plemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0.45 W.

关 键 词：3-D Discrete Wavelet Transform (3-DDWT) Lifting scheme PIPELINING Video coding Low power 

分 类 号：TP911.7[自动化与计算机技术]