基于FPGA的高速双精度浮点乘法器设计  

A High Speed Double Precision Floating Point Multiplier Design Based on FPGA

作　　者：肖鹏[1] 江先阳[2,1] 王高峰[2] 汪波[2] 刘世培[2] 

机构地区：[1]武汉大学物理科学与技术学院,湖北武汉430072 [2]武汉大学微电子与信息技术研究院,湖北武汉430072

出　　处：《微电子学与计算机》2012年第12期17-21,共5页Microelectronics & Computer

基　　金：国家自然科学基金(61072135;60788402);武汉市科技攻关计划项目(201110921295)

摘　　要：设计了一种基于FPGA的高速双精度浮点乘法器.采用了基4Booth算法产生部分积,然后用优化的Wal-lace树阵列结构完成对部分积的累加得到伪和和伪进位,进而对伪和和伪进位采用了部分和并行相加得到最后尾数结果.采用了优化的5级流水线结构的设计在Cyclone Ⅱ EP2C35F672C6器件上经过综合后运行频率可达123.32MHz.在同等优化下,相比于Altera IP核在调用DSP乘法资源情况下运行速度提高大约11%,相比于不调用DSP乘法资源情况下运行速度提高大约67%.To considerably satisfy the requirement, a high speed double precision floating point multiplier based on FPGA is presented. The proposed design adopted radix-4 Booth coder to obtain partial products, then an optimal Wallace tree compression architecture is exploited on these partial products to get a pseudo-sum and pseudo-carry, which are partially accumulated in a parallel approach to generate mantissa of the product. The design with 5-stage pipeline architecture can achieve 123. 32MHz targeted at a Cyclone II EP2C35F672C6 device. By taking the same optimization efforts, the design gets 11% enhancement on operating frequency over an Altera IP core using DSP multipliers, while about 67% over such IP core without using DSP multipliers.

关 键 词：基4Booth编码 双精度浮点数 浮点乘法器 并行结构 流水线结构 WALLACE树 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]