基于System Verilog的SRAM控制器IP核验证  

Verification of SRAM Controller IP Core Based System Verilog

作　　者：周德新[1] 金志威[2] 王鹏[2] 赵学娟[2] 

机构地区：[1]中国民航大学航空自动化学院,天津300300 [2]中国民航大学天津市民用航空器适航与维修重点实验室,天津300300

出　　处：《电子器件》2012年第5期619-622,共4页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目(61179044);中国民航大学校级重点科研项目(CAUC2009ZD0102);中央高校基本科研业务费项目(ZXH2009A001)

摘　　要：随着硬件设计复杂度的提高,设计的后期验证在设计生命周期中占据的比重也越来越大。能否对设计进行全面有效的验证,是验证人员所面临的主要问题。采用SystemVerilog语言对SRAM控制器IP核搭建验证环境,并结合SVA断言技术对其实行监控,得出代码及功能覆盖率数据。通过与传统的验证方法对比分析可知,基于SystemVerilog的验证方法更加全面有效,提高了验证质量。With the improvement of the complexity of the hardware design,the design of the verification is taking up more and more proportion in the design life cycle.It is the main problem faced by the verification engineers to give a comprehensive and efficient verification.The SRAM controller IP core is verified by the SystemVerilog verification environment,and monitored by SystemVerilog assertion technology to get the code and functional coverage data.After comparing and analyzing,the verification method based SystemVerilog is more comprehensive and more efficient than the traditional verification method,so that it improves the quality of verification.

关 键 词：验证 SYSTEM VERILOG 覆盖率 SVA 

分 类 号：TN402[电子电信—微电子学与固体电子学]