基于深亚微米工艺的栅接地NMOS静电放电保护器件衬底电阻模型研究  

A compact model of substrate resistance for deep sub-micron gate grounded NMOS electrostatic discharge protection device

作　　者：吴晓鹏[1] 杨银堂[1] 高海霞[1] 董刚[1] 柴常春[1] 

机构地区：[1]西安电子科技大学微电子学院,宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《物理学报》2013年第4期424-430,共7页Acta Physica Sinica

基　　金：国防预研究基金(批准号:9140A23060111);中央高校基本科研业务费(批准号:K50510250002);陕西省科技统筹创新工程计划(批准号:2011KTCQ01-19)资助的课题~~

摘　　要：在考虑了电导率调制效应的情况下对深亚微米静电放电(electrostatic discharge,ESD)保护器件的衬底电阻流控电压源模型进行优化,并根据轻掺杂体衬底和重掺杂外延型衬底的不同物理机制提出了可根据版图尺寸调整的精简衬底电阻宏模型,所建模型准确地预估了不同衬底结构上源极扩散到衬底接触扩散间距变化对触发电压Vt1的影响.栅接地n型金属氧化物半导体器件的击穿特性结果表明,所提出的衬底电阻模型与实验结果符合良好,且仿真时间仅为器件仿真软件的7%,为ESD保护器件版图优化设计提供了方法支持.The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconduc- tor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.

关 键 词：栅接地n型金属氧化物半导体器件 静电放电 衬底电阻模型 

分 类 号：TN386.1[电子电信—物理电子学]