一种基于FPGA的高速数据通道的实验方法  

An Experimental Method for High-speed Data Channel Based on FPGA

作　　者：郑争兵[1] 魏瑞[1] 陈正涛[1] 

机构地区：[1]陕西理工学院物理与电信工程学院,陕西汉中723003

出　　处：《实验室研究与探索》2012年第12期78-81,共4页Research and Exploration In Laboratory

基　　金：陕西理工学院科研计划资助项目(SLGKY10-14)

摘　　要：为了提高EDA实验教学效果,提出1种基于FPGA的高速数据通道的设计和实验仿真方法。该高速数据通道结构基于乒乓操作的原理,利用Quartus II软件提供的软核双时钟FIFO实现数据的流水式处理。将FPGA作为DSP和数字上变频器AD9857的数据通道构建测试平台,使用嵌入式逻辑分析仪SignalTap II实时获取测试管脚数据,验证设计的正确性。在可靠通信的条件下,FPGA与C6416之间接口数据率达到240 MBps,与AD9857接口的数据率达到22.4 MBps,系统的设计和实验方法简单,可以应用于高速数据流传输的场合。In order to improve the teaching effectiveness of the EDA experiments,a design and experimental simulation method for high-speed data channel based on FPGA was proposed.The high-speed data channel structure which was based on the principle of ping-pong operation used the soft-core dual-clock FIFO provided by Quartus II software to realize flow-through processing of data.The test platform,where FPGA was the data channel between the DSP and the digital up converter AD9857,used the embedded logic analyzer SignalTap II real-time access to data pins to verify the correctness of the design.Under the conditions of reliable communication,the data rate of interface between FPGA and C6416 is 240 MBps and that between FPGA and AD9857 is 22.4 MBps.The design and the experimental method of the system are simple and can be applied to high-speed data streaming applications.

关 键 词：双时钟FIFO FPGA 嵌入式逻辑分析仪 实验教学 

分 类 号：TN92[电子电信—通信与信息系统]