基于SOI工艺下600V LDNMOS的设计与分析  

The design and analysis of 600V LDNMOS based on SOI technology

作　　者：黄世震[1] 翁坤[1] 

机构地区：[1]福州大学福建省微电子集成电路重点实验室,福建福州350002

出　　处：《福州大学学报（自然科学版）》2013年第1期34-37,共4页Journal of Fuzhou University(Natural Science Edition)

摘　　要：基于SOI工艺,运用SILVACO公司的工艺仿真(Athena)和器件仿真(Atlas)模拟软件,结合实际流片测试结果完成对600 V LDNMOS的设计和器件性能分析.整个器件采用环形版图结构,以优化器件的横向尺寸,漏端漂移区通过渐变掺杂技术(VLD)调节器件表面横向电场分布,并在漂移区上方加入一定厚度的槽氧层,从而增大器件的源漏击穿电压.流片测试结果(Vth=1.7 V,Idsat=48 mA,BV=550 V)表明,器件的各项指标基本达到预期目标,实现了设计和分析的目的.Based on the SOI process, using the SILVACO company process （Athena） and devices （Atlas） simulation software, combining with piece of actual flow test results, this thesis aims to complete the design and analysis of device performance of 600V LDNMOS. The entire device adopts a ring structure, to optimize the territory of the lateral dimensions, the drain drift region doping through the gradient transverse electric field distribution of the surface of the technology （VLD） regulating device, and to join a certain thickness of the slot at the top of the drift region oxide layer, to increase the source - drain breakdown voltage of devices. The actual taped test results （ Vth = 1.7 V, Idsat = 48 mA, BV = 550 V） show that the device of the indexes of the device achieve the expected goal of good design and analysis purposes.

关 键 词：SOI LDNMOS 流片 击穿电压 

分 类 号：TU411[建筑科学—岩土工程] TU472.5[建筑科学—土工工程]