屏蔽栅结构射频功率VDMOSFET研制  

Study and Fabrication on RF Power VDMOSFETs with the Gate Shield Structure

作　　者：李飞[1] 刘英坤[1] 邓建国[1] 胡顺欣[1] 孙艳玲[1] 

机构地区：[1]河北半导体研究所

出　　处：《半导体技术》2013年第3期199-202,共4页Semiconductor Technology

摘　　要：在台栅垂直双扩散金属-氧化物-半导体场效应晶体管(VDMOSFET)的结构基础上,利用常规硅工艺技术,研制出了一种具有屏蔽栅结构的射频功率VDMOSFET器件,在多晶硅栅电极与漏极漂移区之间的氧化层中间加入了多晶硅屏蔽层,大幅度降低了器件的栅漏电容Cgd。研制出的屏蔽栅结构VDMOSFET器件的总栅宽为6 cm、漏源击穿电压为57 V、漏极电流为4.3 A、阈值电压为3.0 V、跨导为1.2 S,与结构尺寸相同、直流参数相近的台栅结构VDMOSFET器件相比,屏蔽栅结构VDMOSFET器件的栅漏电容降低了72%以上,器件在175 MHz、12 V的工作条件下,连续波输出功率为8.4 W、漏极效率为70%、功率增益为10 dB。The RF power vertical double diffused metal oxide semiconductor field effect transistor （VDMOSFET） device with the gate shield structure was developed by using standard Si wafer processing technique on the basis of terraced gate VDMOSFET＇ s structure. A polysilicon layer embedded in silicon dioxide located between the polysilicon gate and drain drift region of the device provided a shield of the gate from the drain. The gate-drain capacitance Csd was decreased dramatically. The total gate width of 6 cm, drain-source breakdown voltage of 57 V, drain current of 4.3 A, threshold voltage of 3.0 V, transconductance of 1.2 S have been obtained. Compared to the terraced gate VDMOSFET of the same size and the similar DC parameters, the gate-drain capacitance of the new device is reduced by 72%. The new device can deliver an output power of 8.4 W with the 10 dB power gain and 70% drain efficiency at the conditions of 175 MHz and 12 V operating voltage.

关 键 词：射频垂直双扩散金属-氧化物-半导体场效应晶体管 栅漏电容 栅屏蔽层 台栅结构 屏蔽栅结构 

分 类 号：TN386.1[电子电信—物理电子学]