低功耗0.18μm 10Gbit/s CMOS 1∶4分接器设计  

Design of low-power 10 Gbit/s 1∶4 demultiplexer in 0.18 μm CMOS

作　　者：潘敏[1,2] 冯军[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096 [2]合肥工业大学计算机与信息学院,合肥230001

出　　处：《东南大学学报（自然科学版）》2013年第2期274-278,共5页Journal of Southeast University：Natural Science Edition

基　　金：国家高技术研究发展计划(863计划)资助项目(2011AA10305);国家国际科技合作资助项目(2011DFA11310)

摘　　要：为了实现光纤通信系统中高速分接器低功耗的需求,采用0.18μm CMOS工艺实现了一个全CMOS逻辑10 Gbit/s 1∶4分接器.整个系统采用半速率树型结构,由1∶2分接单元、2分频器单元以及缓冲构成,其中锁存器单元均采用动态CMOS逻辑电路,缓冲由传输门和反相器实现.在高速电路设计中采用CMOS逻辑电路,不但可以减小功耗和芯片面积,其输出的轨到轨电平还能够提供大的噪声裕度,并在系统集成时实现与后续电路的无缝对接.测试结果表明,在1.8 V工作电压下,芯片在输入数据速率为10 Gbit/s时工作性能良好,芯片面积为0.475 mm×0.475 mm,核心功耗仅为25 mW.In order to meet the low-power dissipation requirement of high-speed demultiplexer in optical-fiber-link,a 10 Gbit/s 1∶4 demultiplexer with all-CMOS（complementary metal oxide semiconductor） logic was fabricated by using 0.18 μm CMOS process.The tree-type and half-rate structure was adopted in whole circuit including 1∶2 demultiplexer cells,2 divider cell,buffers for data and clock.The latch cells were implemented by using dynamic CMOS logic circuit.And the buffers were implemented by using the transmission gate and inverter.The CMOS logic circuit can reduce the power dissipation and area.The output rail-to-rail level can offer a high noise margin and implement seamless connection in system integration.The test results of the 1∶4 demultiplexer show that at the supply voltage of 1.8 V,the chip can work well with the input data rate of 10 Gbit/s.The die size is 0.475 mm×0.475 mm and the core power consumption is only 25 mW.

关 键 词：分接器 低功耗 动态CMOS逻辑 

分 类 号：TN432[电子电信—微电子学与固体电子学]