基于Verilog-A的深亚微米GGNMOS ESD保护器件可调模型研究  

A scalable model of deep submicron GGNMOS ESD protection device based on Verilog-A

作　　者：吴晓鹏[1] 杨银堂[1] 董刚[1] 

机构地区：[1]西安电子科技大学微电子学院,宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《兰州大学学报（自然科学版）》2013年第2期270-275,共6页Journal of Lanzhou University(Natural Sciences)

基　　金：国防预研究基金项目(9140A23060111);陕西省科技统筹创新工程计划项目(2011KTCQ01-19);中央高校基本科研业务费专项资金项目

摘　　要：针对深亚微米工艺实现的GGNMOS器件推导分析了其相关寄生元件的工作机理和物理模型,并基于Verilog-A语言建立了保护器件的电路仿真模型.详细讨论了保护器件寄生衬底电阻对保护器件触发电压的影响,进一步给出了衬底电阻值可随源极扩散到衬底接触扩散间距调节的解析表达式并用于特性模拟,仿真结果与流片器件的传输线脉冲测试结果吻合.The characteristics and physical models of the parasitic elements of deep submicron GGNMOS were first derived and a model of the protection device for circuit simulation was built using Verilog-A language. The impact of the parasitic substrate resistance on the trigger voltage of the protection device was discussed in detail. Then, a model of substrate resistance scalable with the source contact to bulk contact distance was derived and used for the simulation, whose results coincide with the transmission line pulsing measurement results of the GGNMOS tape-out.

关 键 词：栅接地NMOS 静电放电 衬底电阻 传输线脉冲 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN406