H型栅SOIMOS作为静电保护器件的维持电压的研究(英文)  

Investigation on Holding Voltage of H-gate SOI MOS as ESD Protection Device

作　　者：姜一波[1] 曾传滨[1] 罗家俊[1] 韩郑生[1] 

机构地区：[1]硅器件及集成技术研究室,中国科学院微电子研究所,北京100029

出　　处：《固体电子学研究与进展》2013年第2期108-111,共4页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(60927006)

摘　　要：对绝缘体上硅工艺来说,静电保护可靠性是一个关键且具有挑战性的问题。着重于研究H型栅SOIMOS的维持电压,通过实验发现此器件的维持电压与栅宽紧密联系。结合TCAD仿真解释了器件的工作机理,通过建立集约模型并由HSPICE仿真,揭示了体电阻与维持电压之间的关系。Electrostatic discharge reliability is a vital and challenging issue for SOI （Silicon on insulator） technology. The paper focused on holding voltage on which latch up risk depends di- rectly for H-gate SOI MOS. A new phenomenon was indicated that among investigated device pa- rameters the gate width affected holding voltage strongly also. Then the device operating mecha- nism was discussed through TCAD simulations. Combining with a compact model and HSPICE simulations the relationship between bulk resistor and holding voltage was revealed finally.

关 键 词：绝缘体上硅 静电保护 维持电压 

分 类 号：TN386[电子电信—物理电子学]