一种高效双精度浮点乘法器  

An Efficient Double-precision Floating-point Multiplier

作　　者：夏炜[1] 肖鹏[1] 

机构地区：[1]武汉大学物理科学与技术学院,武汉430072

出　　处：《计算机测量与控制》2013年第4期1017-1020,共4页Computer Measurement &Control

基　　金：国家自然科学基金(61072135;60788402);武汉市科技攻关计划项目(201110921295)

摘　　要：浮点乘法器(FPM)是中央处理器的关键部件之一,因此其性能是处理器的关键影响因素之一,高性能浮点乘法器是研究人员的追求;基于此需求,提出了一种高速双精度浮点乘法器,该设计采用了有别于传统基2Booth算法,即基4Booth算法产生部分积,在此基础上用优化的Wallace树阵列结构进行部分积的累加得到和序列和进位序列,进而对和序列和进位序列采用部分和并行相加得到最后尾数结果;采用了优化的10级流水线结构的设计在Cyclone II EP2C15AF484C6器件上实现后运行频率可达138.77MHz;在同等优化努力下,相比于Altera IP核运行速度提高大约67.77%;类似的,在Xilinx Virtex2 xc2v6000上的实现比现存的设计频率提高约102.2%;实验结果显示了所设计FPM结构的有效性。Floating point multiplier （FPM） is one key part for CPU, its performance plays a great role in CPU performance, thus a high performance FPM attracts much attention all over the world. To considerably satisfy the requirement, a high speed double precision FPM is presented. The proposed design adopted radix-4 Booth coder to obtain partial products, then an optimal Wallace tree compression architec-ture is exploited on these partial products to obtain a pseudo-sum and pseudo-carry, which are partially accumulated in a parallel approach to generate mantissa of the product. Its radix-4 Booth coder is different from the conventionally adopted radix-2 Booth coder. The design with 10-stage pipeline architecture can achieve up to 138.77MHz targeted at a Cyclone II EP2C15AF484C6 device. By taking the same opti-mization efforts and the same stage pipeline, the design reaches about 67.77% enhancement on operating frequency over an Altera IP core. Similarly, running frequency targeted at Xilinx Virtex2 xe2v6000 increased about 102.2% when compared to an existing design. The experi-mental results demonstrate the efficiency of the proposed FPM architecture.

关 键 词：基4Booth编码 双精度浮点数 浮点乘法器 并行结构 流水线结构 WALLACE树 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]