基于存储级并行的同时多线程电压紧急容错技术  

Mitigating Voltage Emergency in Simultaneous Multithreading Processor by Memory Level Parallelism Aware Thread Scheduling

作　　者：胡杏[1,2] 潘送军[1,2] 胡瑜[1] 李晓维[1] 

机构地区：[1]中国科学院计算技术研究所计算机体系结构国家重点实验室,北京100190 [2]中国科学院大学,北京100049

出　　处：《计算机学报》2013年第5期1065-1075,共11页Chinese Journal of Computers

基　　金：国家自然科学基金(61076018;61274030);国家"九七三"重点基础研究发展规划项目基金(2011CB302503)资助~~

摘　　要：时钟门控等低功耗技术引起的电流波动以及供电网络上的寄生阻抗效应,共同形成感应噪声(di/dt),引起供电电压波动.过大的电压波动可能引发时延故障并影响系统正确运行,被称之为电压紧急.文章分析了同时多线程处理器中电压紧急与程序访存行为之间的关系,结合程序的存储级并行性,提出了一种线程调度方法以减少电压紧急对系统性能的影响.实验结果表明,与flush方法相比,所提方法在双线程环境下平均减少21.7%的电压紧急,在四线程环境下平均减少25.2%的电压紧急,并能够有效提高同时多线程处理器的公平性.Low power design techniques like clock gating incur side-effect of increasing current variation drawn by processors. Current variation produces voltage ripples due to parasitic induct- ance in power supply networks. Voltage emergency occurs when voltage drops below threshold, which may result in system malfunction because of timing faults. This work characterized the re- lationship between voltage emergencies and memory access behaviors in simultaneous mul- tithreading processors. And then proposed a thread scheduling strategy utilizing memory level parallelism to mitigate voltage emergencies. Experimental results show that, compared with ex- isting work, the proposed strategy reduces voltage emergencies by 21.7% and 25.2% for 2-thread workloads and 4-thread workloads respectively, and achieves better overall balance between performance and fairness.

关 键 词：电压紧急 感应噪声 同时多线程 存储级并行 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]