MOS器件中的边界陷阱  

Border Traps in MOS Devices

作　　者：王永强[1] 何宝平[1] 张正选[1] 

机构地区：[1]西北核技术研究所,西安710024

出　　处：《微电子学与计算机》2000年第4期37-41,共5页Microelectronics & Computer

摘　　要：文章主要介绍了ＭＯＳ器件中边界陷阱的特点、性能、形成机理及对器件性能的影响。给出了二种边界陷阱的理论模型，阐述了它的微观结构，研究发现快、慢二种边界陷阱有着不同的缺陷结构，同时还讨论了Ｃ－Ｖ测试技术和ＤＴＢＴ测试技术二种测量边界陷阱的方法，最后论述了边界陷阱的退火效应以及与界面态陷阱和氧化物陷阱的联系与区别，并对所得出结果进行了讨论。This paper mainly introduce the characteristic, properties and forming mechanism of border traps and their effects on MOS devices performance reported abroad. Two kinds of theoretical models for border traps and their possible microscopic natures are presented. It is shown that the effect are different for fast border traps and slow border traps. Two measuring techniques C-V test and DTBT for border traps are discussed. Finally, border traps annealing effects and their correlation with oxide traps and interface traps are demonstrated.

关 键 词：边界陷阱 缺陷结构 DTBT MOS器件 

分 类 号：TN386.1[电子电信—物理电子学]