模式可配置的NAND Flash纠错系统设计与实现  

Design and implementation of mode reconfigurable NAND flash error correcting system

作　　者：徐富新[1] 刘应[1] 刘雁群[1] 向超[1] 

机构地区：[1]中南大学物理与电子学院,湖南长沙410083

出　　处：《中南大学学报（自然科学版）》2013年第5期1918-1925,共8页Journal of Central South University:Science and Technology

基　　金：国家自然科学基金资助项目(61178017)

摘　　要：针对NAND flash存储器设计一种模式可配置的纠错系统的电路结构,该结构可以预防错误位数大于设计纠错位数的情况发生。提出一种高速并行BCH编译码的电路设计方法,并导出一种无需有限域求逆运算的BM迭代算法的硬件实现方法。通过复用编码算法电路与译码算法电路,同时结合流水线技术与乒乓操作技术,实现以较小的硬件资源开销提高纠错系统性能。该纠错系统电路在EP4CE15E22C8系列FPGA芯片上实现,并进行测试分析。测试结果表明:在相同的系统工作频率下,该纠错系统电路的数据吞吐率是传统串行纠错电路的8倍,而硬件资源开销只增加1倍;与传统的NAND flash纠错电路相比,该纠错电路结构相对独立,可移植性强,可满足多种应用场合的需要。Mode reconfigurable error correcting circuit was presented for NAND flash memory. This circuit can effectively avoid larger error bits than the designed error correcting bits. Hereinafter, a circuit design method of parallel BCH code was brought up, and a kind of BM iterative algorithm hardware implementation was deduced without finite field inverse operation. Based on the multiplexing technology of the codec algorithm circuit and combing pipeline technology with ping-pong operation technology, the performance of the correcting system is improved ingeniously while the increase of the cost is acceptable. The error correcting system circuit is implemented and tested in the FPGA chip of the EP3CE15E22C8 series. Under the same system operating frequency, eight times greater data throughput rate are achieved than those of the traditional serial circuits with only double hardware cost. In comparison with traditional NAND flash error correcting circuit, the present error correcting circuit is relatively independent and portable, and can meet the requirement of several applications.

关 键 词：NAND FLASH存储器 纠错电路 可配置模式 BCH码 现场可编程门阵列 

分 类 号：TP919.3[自动化与计算机技术]