小数乘法器的低功耗设计与实现  

Low-Power Design and Application for Decimal Multiplier

作　　者：袁博[1] 刘红侠[1] 

机构地区：[1]西安电子科技大学宽禁带半导体材料与器件国家重点实验室,西安710071

出　　处：《数据采集与处理》2013年第3期376-381,共6页Journal of Data Acquisition and Processing

基　　金：国家自然科学基金(60976068)资助项目;教育部科技创新工程重大项目培育资金(708083)资助项目;教育部博士点基金(200807010010)资助项目

摘　　要：提出一种针对小数乘法器的低功耗设计算法,其优化指标为综合后小数乘法器内部寄存中间运算结果的寄存器位宽,解决了目前低功耗设计中算法自身逻辑单元被引入系统从而降低系统优化效果的问题。该算法能够在不降低系统工作效率、不损失系统运算精度、不增加额外逻辑单元的条件下,大幅降低系统功耗和面积。在使用该算法对某一射频模块进行优化后,硬件测试结果显示该射频模块对某型号FPGA的逻辑占用率相比优化前降低17.9%,寄存器总数降低30.7%,存储单元占用率降低21.5%。该算法适用于对含有大量小数乘法运算的系统进行低功耗优化。A low-power design methodology is presented for decimal multiplier, the methodolo- gy optimization object is the width of the adders in synthesized multiplier. The methodology resolves the problem of optimization logic ioining into optimized system existed in present low- power design. It can reduce system power and area significantly without additional logic, and the system working efficiency and calculation accuracy are remained. After optimizing a radio- frequency circuit using the proposed method, FPGA test result shows that logic utilization is reduced by 17.9%, total registers number is reduced by 30.7%, and total block memory bits utilization is reduced by 21.5~. The methodology perform well in the system optimization, including the optimization of large-scale multipliers.

关 键 词：小数乘法器 低功耗设计 数据宽度 优化逻辑 

分 类 号：TN702[电子电信—电路与系统] TN402